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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MCM69P817
256K x 18 Bit Pipelined BurstRAMTM Synchronous Fast Static RAM
The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2-bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive- edge-triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P817 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as "a" and "b". SBa controls DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge-triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM69P817 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. * MCM69P817 Speed Options
Speed 200 MHz 180 MHz 166 MHz tKHKH 5 ns 5.5 ns 6 ns Pipelined tKHQV 2.5 ns 3.0 ns 3.5 ns Setup 0.5 ns 0.5 ns 0.5 ns Hold 1 ns 1 ns 1 ns IDD 475 mA 450 mA 425 mA Pkg PBGA PBGA PBGA ZP PACKAGE PBGA CASE 999-01
* 3.3 V + 10%, - 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply * ADSP, ADSC, and ADV Burst Control Pins * Selectable Burst Sequencing Order (Linear/Interleaved) * Single-Cycle Deselect Timing * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * PB1 Version 2.0 Compatible * JEDEC Standard 119-Pin PBGA Package
BurstRAM is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. 6/10/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM69P817 1
FUNCTIONAL BLOCK DIAGRAM
LBO ADV K ADSC ADSP K2
BURST COUNTER CLR 2
2
18 256K x 18 ARRAY
SA SA1 SA0
ADDRESS REGISTER
18
16
SGW SW SBa WRITE REGISTER b 2 WRITE REGISTER c
18
18
DATA-IN REGISTER K
DATA-OUT REGISTER
SBb
K2
K
SE1 SE2 SE3 G
ENABLE REGISTER
ENABLE REGISTER
DQa - DQb
MCM69P817 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
1 A B C D E NC F G NC H J K L M VDDQ DQb N P R T NC U VDDQ SA NC SA NC NC NC SA NC SA NC NC VDDQ DQb NC NC NC DQb SA VSS VSS VSS LBO SW SA1 SA0 VDD VSS VSS VSS NC NC DQa NC SA VDDQ NC DQa NC DQb DQb NC SBb VSS NC VSS VSS ADV SGW VDD K NC VSS VSS NC VSS SBa NC DQa DQa NC VDDQ DQb NC VDDQ NC NC DQb 2 SA SE2 SA NC 3 SA SA SA VSS VSS VSS 4 ADSP ADSC VDD NC SE1 G 5 SA SA SA VSS VSS VSS 6 SA SE3 SA DQa NC 7 VDDQ NC NC NC DQa
DQa VDDQ
VDDQ VDD NC DQb DQb NC
VDD VDDQ NC DQa DQa NC
TOP VIEW 119 BUMP PBGA Not to Scale
MOTOROLA FAST SRAM
MCM69P817 3
PBGA PIN DESCRIPTIONS
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address used to initiate a new READ or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G and LBO. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
4A
ADSP
Input
4G (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 4F
ADV DQx G
Input I/O Input
4K 3R
K LBO
Input Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4N, 4P
SA SA1, SA0
Input Input
5L, 3G (a) (b) 4E
SBx SE1
Input Input
2B 6B 4H
SE2 SE3 SGW
Input Input Input
4M
SW
Input
4C, 2J, 4J, 6J, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U
VDD VDDQ VSS NC
Supply Supply Supply --
MCM69P817 4
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 Through 5)
Next Cycle Deselect Deselect Deselect Deselect Deselect Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Continue Write Continue Write Suspend Write Suspend Write Address Used None None None None None External External Next Next Next Next Current Current Current Current External Next Next Current Current SE1 1 0 0 X X 0 0 X X 1 1 X X 1 1 0 X 1 X 1 SE2 X X 0 X 0 1 1 X X X X X X X X 1 X X X X SE3 X 1 X 1 X 0 0 X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 X 0 0 1 1 G3 X X X X X X X 1 0 1 0 1 0 1 0 X X X X X DQx High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ High-Z DQ High-Z DQ High-Z DQ High-Z High-Z High-Z High-Z High-Z Write 2, 4 X X X X X X5 READ5 READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE
NOTES: 1. X = don't care. 1 = logic high. 0 = logic low. 2. Write is defined as either (a) any SBx and SW low or (b) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
WRITE TRUTH TABLE
Cycle Type Read Read Write Byte a Write Byte b Write All Bytes Write All Bytes SGW H H H H H L SW H L L L L X SBa X H L H L X SBb X H H L L X
MOTOROLA FAST SRAM
MCM69P817 5
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage (See Note 2) Input Voltage Relative to VSS for Any Pin Except VDD (See Note 2) Input Voltage (Three-State I/O) (See Note 2) Output Current (per I/O) Package Power Dissipation (See Note 3) Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD Tbias Tstg Value VSS - 0.5 to + 4.6 VSS - 0.5 to VDD VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDDQ + 0.5 20 1.6 - 10 to 85 - 55 to 125 Unit V V V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing can not be controlled and is not allowed. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS -- PBGA
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single Layer Board Four Layer Board Symbol RJA RJB RJC Max 41 19 11 9 Unit C/W C/W C/W Notes 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM69P817 6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(3.6 V VDD 3.135 V, 70C TA 0C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Ambient Temperature Input Low Voltage Input High Voltage VIH Symbol VDD VDDQ TA VIL VIH Min 3.135 2.375 0 - 0.3 2.0 Typ 3.3 3.3 -- -- -- Max 3.6 VDD 70 0.8 VDD + 0.3 Unit V V C V V
VSS
VSS - 1.0 V
20% tKHKH (MIN)
Figure 1. Undershoot Voltage DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD and VDDQ MCM69P817-2.5 MCM69P817-3 MCM69P817-3.5 Symbol Ilkg(I) Ilkg(O) IDDA Min -- -- -- Typ -- -- -- Max 1 1 475 450 425 40 Unit A A mA 2, 3, 4 Notes 1
CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V) TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at Vin VIL or VIH) Clock Running (Device Deselected, MCM69P817-2.5 Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V) Static Clock Running (Device Deselected, MCM69P817-2.5 Freq = Max, VDD = Max, All Inputs Static at Vin VIL or VIH) Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V Output High Voltage (IOH = - 2 mA) VDDQ = 2.5 V Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V
ISB2
--
--
mA
5
ISB3 ISB4
-- --
-- --
45 190
mA mA
5 5
ISB5 VOL1 VOH1 VOL2
-- -- 1.7 --
-- -- -- --
85 0.7 -- 0.4
mA V V V V
5
Output High Voltage (IOH = - 4 mA) VDDQ = 3.3 V VOH2 2.4 -- -- NOTES: 1. LBO pin has an internal pullup and will exhibit leakage currents of 5 A. 2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr / tf, pulse level 0 to 3.0 V). 3. All addresses transition simultaneously low (LSB) and then high (MSB). 4. Data states are all zero. 5. Device in Deselected mode as defined by the Truth Table.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 70C TA 0C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 4 7 Max 5 8 Unit pF pF
MOTOROLA FAST SRAM
MCM69P817 7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(3.6 V VDD 3.135 V, 70C TA 0C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Slew Rate (See Figure 3) . . . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted Output Rise/Fall Times (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 ns
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM69P817-2.5 200 MHz Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address Data In Write Chip Enable ADSP, ADSC, ADV Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tADKH tDVKH tWVKH tEVKH tADSKH tKHAX tKHADSX tKHDX tKHWX tKHEX Min 5 2.2 2.2 -- -- 0 1.5 0 -- 1.5 0.5 0.5 0.5 0.5 1.5 1.0 Max -- -- -- 2.5 3.5 -- -- -- 3.5 5 -- MCM69P817-3 180 MHz Min 5.5 2.5 2.5 -- -- 0 1.5 0 -- 1.5 0.5 0.5 0.5 0.5 1.5 1.0 Max -- -- -- 3 3.5 -- -- -- 3.5 5.5 -- MCM69P817-3.5 166 MHz Min 6 2.7 2.7 -- -- 0 1.5 0 -- 1.5 0.5 0.5 0.5 0.5 1.5 1.0 Max -- -- -- 3.5 3.8 -- -- -- 3.8 6 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 3, 4 3, 4 3 3 3, 5, 6 3, 6 3, 5, 6 3, 5, 6 3, 5, 6 3 Notes N
Hold Times:
--
--
--
ns
3
NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. Tested per AC Test Load, Figure 2. 4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 5. Measured at 200 mV from steady state. 6. This parameter is sampled and not 100% tested.
MCM69P817 8
MOTOROLA FAST SRAM
OUTPUT Z0 = 50 RL = 50 1.5 V
Figure 2. AC Test Load
OUTPUT LOAD
OUTPUT BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.4 0.4 2.4 0.4
OUTPUT WAVEFORM
2.4 0.4 tf
2.4 0.4
tr NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.4 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.4 V unloaded.
Figure 3. Unloaded Rise and Fall Time Characterization
MOTOROLA FAST SRAM
MCM69P817 9
3.6
3.135 PULL-UP VOLTAGE (V) - 0.5 0 1.4 1.65 2.0 3.135 3.6 I (mA) MIN - 40 - 40 - 40 - 37 - 28 0 0 I (mA) MAX - 120 - 120 - 120 - 104 1.4 - 81 - 20 0 0 0 - 40 CURRENT (mA) - 120 VOLTAGE (V) VOLTAGE (V) 2.8
1.65
(a) Pull-Up for 3.3 V I/O Supply
2.9 2.5 PULL-UP VOLTAGE (V) - 0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 I (mA) MIN - 26 - 26 - 26 - 18 - 14 0 0 0 I (mA) MAX - 75 - 75 - 75 - 58 - 49 - 21 -7 0 0 0 - 26 CURRENT (mA) - 75 2.3 2.1
1.25 0.8
(b) Pull-Up for 2.5 V I/O Supply
VDD PULL-DOWN VOLTAGE (V) - 0.5 0 0.5 1 1.65 1.8 3.6 4 I (mA) MIN - 34 0 17 35 45 46 46 46 I (mA) MAX - 126 0 47 90 114 120 120 120 0.3 0 0 46 CURRENT (mA) 120 VOLTAGE (V) 1.8 1.65
(c) Pull-Down for 3.3 V and 2.5 V I/O Supply Figure 4. Typical Output Buffer Characteristics
MCM69P817 10
MOTOROLA FAST SRAM
READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
MOTOROLA FAST SRAM
B C D t KHQV BURST WRAPS AROUND Q(A) tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE D(C) D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ
SA
A
ADSP
ADSC
ADV
SE1
E
W
G
t KHQV
DQx
Q(n)
tKHQZ
tKHQX1
DESELECTED
SINGLE READ
MCM69P817 11
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
APPLICATION INFORMATION
STOP CLOCK OPERATION In the stop clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADSP and ADSC, and stops the clock after the last write data is latched, or the last read data is driven out. When starting and stopping the clock, the AC clock timing and parametrics must be strictly maintained. For example, clock pulse width and edge rates must be guaranteed when starting and stopping the clocks. To achieve the lowest power operation for all three stop clock modes, stop read, stop write, and stop deselect: * Force the clock to a low state. * Force the control signals to an inactive state (this guarantees any potential source of noise on the clock input will not start an unplanned on activity). * Force the address inputs to a low state.
STOP CLOCK WITH READ TIMING
K
ADSP
ADDRESS
A1
A2
ADV
DQx
Q(A1)
Q(A1+1)
Q(A2)
ADSP (INITIATES BURST READ)
CLOCK STOP (CONTINUE BURST READ)
WAKE UP ADSP (INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL). Best results are obtained if VIL < 0.2 V.
MCM69P817 12
MOTOROLA FAST SRAM
STOP CLOCK WITH WRITE TIMING
K
ADSC
ADDRESS
A1
A2
WRITE
ADV
DATA IN
D(A1)
D(A1+1)
VIH OR VIL FIXED (SEE NOTE)
D(A2)
HIGH-Z DQx ADSC (INITIATES BURST WRITE) CLOCK STOP (CONTINUE BURST WRITE) WAKE UP ADSC (INITIATES BURST WRITE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state.
MOTOROLA FAST SRAM
MCM69P817 13
STOP CLOCK WITH DESELECT OPERATION TIMING
K
ADSC
SE1
DATA IN
VIH OR VIL FIXED (SEE NOTE 1)
HIGH-Z DQx DATA DATA
CONTINUE BURST READ
CLOCK STOP (DESELECTED)
WAKE UP (DESELECTED)
NOTES: 1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state. 2. For best possible power savings, the data-in should be driven low.
MCM69P817 14
MOTOROLA FAST SRAM
NON-BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC- based and other high end MPU-based based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM69P817. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 5.
CONTROL PIN TIE VALUES (H VIH, L VIL)
Non-Burst Sync Non-Burst, Pipelined SRAM ADSP H ADSC L ADV H SE1 L LBO X
NOTE: Although X is specified in the table as a don't care, the pin must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Configured as Non-Burst Synchronous SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
69P817
XX
X
X
Blank = Trays, R = Tape and Reel Speed (2.5 = 2.5 ns, 3 = 3.0 ns, 3.5 = 3.5 ns) Package (ZP = PBGA)
Full Part Numbers -- MCM69P817ZP2.5 MCM69P817ZP2.5R
MCM69P817ZP3 MCM69P817ZP3R
MCM69P817ZP3.5 MCM69P817ZP3.5R
MOTOROLA FAST SRAM
MCM69P817 15
PACKAGE DIMENSIONS
ZP PACKAGE 7 x 17 BUMP PBGA CASE 999-01
4X PIN 1A IDENTIFIER
0.20 (0.008)
A -W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER.
7 6 54 3 2 1 A B C D E F G H J K L M N P R T U
P
B -L-
S
16X
G
DIM A B C D E F G K N P R S 119X
MILLIMETERS MIN MAX 14.00 BSC 22.00 BSC --- 2.40 0.60 0.90 0.50 0.70 1.30 1.70 1.27 BSC 0.80 1.00 11.90 12.10 19.40 19.60 7.62 BSC 20.32 BSC
INCHES MIN MAX 0.551 BSC 0.866 BSC --- 0.094 0.024 0.035 0.020 0.028 0.051 0.067 0.050 BSC 0.031 0.039 0.469 0.476 0.764 0.772 0.300 BSC 0.800 BSC
N TOP VIEW
6X
G R BOTTOM VIEW
D 0.30 (0.012) 0.10 (0.004)
S S
TW T
S
L
S
F C
0.25 (0.010) T 0.35 (0.014) T 0.15 (0.006) T -T- K E SIDE VIEW
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 303-675-2140 or 1-800-441-2447 MfaxTM : RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 - US & Canada ONLY 1-800-774-1848 INTERNET : http: / / motorola.com/sps JAPAN: Nippon Motorola Ltd.; SPD, Strategic Planning Office; 4-32-1, Nishi-Gotanda; Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MCM69P817 16
MCM69P817/D MOTOROLA FAST SRAM

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